Circuit characterization is a process of capturing a circuit performance and representing the same as a black box model. SPICE simulations are performed for various input slew and output load combinations for the timing/power arcs identified from functionality and results are typically captured as a liberty model. This liberty model provides information on circuit performance such as delays, transition time, power and input capacitance.
The liberty model captures the performance of the circuit using lookup tables with delays specified as a function of input slew and output load. Generally, these lookup tables are created for different timing arcs. A timing arc is defined as a path to an output pin from a related input pin. It is possible to have different timing arcs for the same input pin and output pin pair. In such cases, the timing arcs are differentiated by specifying the state under which each timing arc is valid. A state is defined by specifying secondary pins' combination for the selected timing arc.
Traditional characterization tools accept functionality in the form of a truth table or Boolean expression and generate timing arcs. However, current techniques do not provide provisions for generating optimum state dependent timing arcs. The user is expected to explicitly specify state dependent timing arcs that need to be included in the liberty model.
The algorithm used by the current characterization tools to generate dependent timing arcs is explained using a sample truth table for a 4-1 MUX. Since the full truth table contains 64 entries, for simplicity, only few entries are used in the table for illustrating the functionality of the 4-1 MUX.
TABLE 1S1S0ABCD:Y. . .. . .. . .. . .. . .. . .. . .. . .000001:0000010:0000100:0001000:1. . .. . .. . .. . .. . .. . .. . .. . .010001:0010010:0010100:1011000:0. . .. . .. . .. . .. . .. . .. . .. . .100001:0100010:1100100:0101000:0. . .. . .. . .. . .. . .. . .. . .. . .110001:1110010:0110100:0111000:0. . .. . .. . .. . .. . .. . .. . .. . .
Even though there may be multiple states for a timing arc, not all states are necessary to capture the circuit performance because of the presence of redundant arcs. Generally, redundant arcs are created by those states which do not affect the output transition for a particular input transition. For example, it can be seen from the above table 1 for the case of 4-1 MUX, the timing arc from input pin A to output pin Y is valid only if the select pin S1 and S0 are held low. Thus for the arc A-Y, any state with ( S1·S0), (S1· S0) and (S1·S0) are redundant.
For ( S1· S0), the conditions of the secondary pins B, C or D do not affect the output transition at pin Y for a transition at the input pin A. Thus pins B, C and D are at “don't care” (hereafter denoted by X) condition. This means that there can only be one timing arc from input pin A to output pin Y which implies that there are no states associated with this timing arc other than the one where S1 and S0 are held low. Consequently, the liberty model needs to have only one entry for the timing arc from pin A to pin Y. The timing arcs from pins B, C and D to pin Y are deduced similarly.
For the pins S1 and S0, the determination of states is not as simple. Consider the arc S1 to Y. There are 32 possible states for this arc. Some of these arcs have positive unate timing sense and some have negative unate timing sense. Binary numbers 01100 are used to represent state S0·A·B· C· D. For the arc under consideration, consider the states 00010, 00011, 00110 and 00111. For each of these states, S1 changing from high to low or low to high causes a change in Y in the same direction. Thus the timing sense is positive unate. It can be seen from the table 2 that pins B and D have no effect on the transition at pin Y for a transition at pin S1. Thus the 4 states can be reduced to one state, i.e., to ( S0·Ā·C) as shown in the following table 2 for arc S1−Y for state 00×1×. It can be seen in the following table 2 that this gives a positive unate arc for the state ( S0·Ā·C).
TABLE 2S1S0ABCD:Y000010:0000011:0000110:0000111:0100010:1100011:1100110:1100111:1
In the above table 2, consider the same arc for a different set of states 10001, 10011, 11001, and 11011 and it can be seen that even in this case, a change in S1 causes a change in Y in the same direction. However, in this case, it is a different set of pins that are at X. For these four states, it can be seen in the following table 3 that the pins A and C have no effect on the transition at pin Y for a transition at pin S1. Consequently, the four states can be reduced to one state, i.e., (S0· B·D). Further, it can be seen in the following table 3 that the two states ( S0·Ā·C) and (S0· B·D) cannot be simplified any further and constitute two valid states for the arc from input pin S1 to output pin Y for the same timing sense. There are two more states for the arc S1−Y with negative unate timing sense which can be derived in a similar manner as shown in the following tables 4 and 5. Table 4 illustrates arc S1−Y for state 01×0×, which gives a negative unate arc with the state ( S0·A· C). Table 5 illustrates arc S1−Y for state 1×1×0, which gives a negative unate arc for state (S0·B· D).
TABLE 3S1S0ABCD:Y010001:0010011:0011001:0011011:0110001:1110011:1111001:1111011:1
TABLE 4S1S0ABCD:Y001000:1001001:1001100:1001101:1101000:0101001:0101100:0101101:0
TABLE 5S1S0ABCD:Y010100:1010110:1011100:1011110:1110100:0110110:0111100:0111110:0
It can be seen from the above tables 2-5 that even though there may be multiple states for a timing arc, not all states are necessary to capture the circuit performance because of the presence of redundant arcs. Using current circuit characterization techniques can result in creating such redundant arcs including those states which may not affect the output transition for an associated input transition. Further, the current circuit characterization techniques fail to produce a truth table that includes substantially only the valid arcs for each pin in a circuit. Furthermore, identifying valid timing arcs and states associated with each pin is generally crucial for circuit characterization.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.